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Programmable 360 Inclinometer ADIS16203
FEATURES
0 to 360 Inclinometer 180 output format option 14-bit digital inclination outputs Linear output, 0.025 resolution 12-bit digital temperature sensor output Digitally controlled bias calibration Digitally controlled sample rate Digitally controlled filtering Digitally controlled direction/orientation Dual alarm settings with rate/threshold limits Auxiliary digital I/O Digitally activated self-test Digitally activated low power mode SPI(R)-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: 3.0 V to 3.6 V 3500 g powered shock survivability
angle data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI interface provides access to multiple measurements: 360 linear inclination angles, 180 linear incline angles, temperature, power supply, and one auxiliary analog input. Easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single-command offset calibration, along with convenient sample rate and bandwidth control. The ADIS16203 offers the following embedded features that eliminate the need for external circuitry and provide a simplified system interface: * * * * * Configurable alarm function Auxiliary 12-bit analog-to-digital converter (ADC) Auxiliary 12-bit digital-to-analog converter (DAC) Configurable digital I/O port Digital self-test function
APPLICATIONS
Tilt sensing, inclinometers Platform control, stabilization, and leveling Motion/position measurement Monitor/alarm devices (security, medical, safety) Robotics
GENERAL DESCRIPTION
The ADIS16203 is a complete incline-angle measurement system in a single compact package enabled by the Analog Devices, Inc., iSensorTM integration. By enhancing the Analog Devices iMEMS(R) sensor technology with an embedded signal processing solution, the ADIS16203 provides factory-calibrated, sensor-to-digital incline-
The ADIS16203 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16203 is available in a 9.2 mm x 9.2 mm x 3.9 mm laminate-based land grid array (LGA) package with a temperature range of -40C to +125C.
FUNCTIONAL BLOCK DIAGRAM
AUX ADC AUX DAC VREF
ADIS16203
TEMPERATURE SENSOR CS SPI PORT SCLK DIN SELF-TEST VDD DIGITAL CONTROL DOUT
INERTIAL MEMS SENSOR
SIGNAL CONDITIONING AND CONVERSION
CALIBRATION AND DIGITAL PROCESSING
POWER MANAGEMENT
ALARMS
AUXILIARY I/O
COM AUX COM RST DIO0 DIO1
06108-001
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADIS16203 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performace Characteristics................................................ 8 Theory of Operation ...................................................................... 11 Output Response ........................................................................ 11 Temperature Sensor ................................................................... 11 Basic Operation............................................................................... 12 Serial Peripheral Interface (SPI) ............................................... 12 Data Output Register Access..................................................... 13 Programming and Control............................................................ 14 Control Register Overview........................................................ 14 Control Register Access ............................................................. 14 Control Register Details................................................................. 15 Calibration................................................................................... 15 Calibration Register Definition.................................................15 Alarms ..........................................................................................15 Sample Period Control ...............................................................18 Filtering Control .........................................................................18 Power-Down Control .................................................................19 Status Feedback ...........................................................................20 COMMAND Control.................................................................20 Miscellaneous Control Register ................................................21 Peripherals........................................................................................22 Auxiliary ADC Function ...........................................................22 Auxiliary DAC Function............................................................22 General-Purpose I/O Control ...................................................23 Applications .....................................................................................24 Hardware Considerations ..........................................................24 Grounding and Board Layout Recommendations .................24 Self-Test Tips ...............................................................................24 Band Gap Reference ...................................................................24 Power-On Reset Operation .......................................................25 Second-Level Assembly..............................................................25 Example Pad Layout ...................................................................25 Outline Dimensions........................................................................26 Ordering Guide ...........................................................................26
REVISION HISTORY
8/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADIS16203 SPECIFICATIONS
TA = -40oC to +125C, VDD = 3.3 V, tilt = 0, unless otherwise noted. Table 1.
Parameter INCLINOMETER 1 Input Range Relative Accuracy Sensitivity Accuracy Temperature Coefficient NOISE PERFORMANCE Output Noise Noise Density FREQUENCY RESPONSE Sensor Bandwidth Sensor Resonant Frequency SELF-TEST STATE Output Change When Active TEMPERATURE SENSOR Output at 25C Scale Factor ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Input Capacitance, CIN Conditions Min Typ 360 0.6 0.025 0.0167 1.0 0.1 0.037 Max Unit Degrees Degrees Degrees/LSB Degrees/C Degrees rms Degrees rms Degrees/Hz rms Hz kHz Degrees LSB LSB/C Bits LSB LSB LSB LSB V pF V mV ppm/oC Bits LSB LSB mV % V s V V A A pF
25C, maximum filter setting 25C
At 25C, no averaging At 25C, maximum averaging At 25C, no averaging
2250 5.5 At 25C 34 1278 -2.13 12 2 1 4 2 0 During acquisition At 25C -10 40 70 5 k/100 pF to GND For Code 101 to Code 4095 12 4 1 5 0.5 0 to 2.5 2 10 2.0 VIH = VDD VIL = 0 V 0.2 -40 10 0.8 1 -60 20 2.5 +10 2.5
Rev. 0 | Page 3 of 28
ADIS16203
Parameter DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period 2 FLASH MEMORY Endurance 3 Data Retention 4 CONVERSION RATE Minimum Conversion Time Maximum Conversion Time Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range VDD Power Supply Current Conditions ISOURCE = 1.6 mA ISINK = 1.6 mA Min 2.4 0.4 0.5 20,000 20 244 484 4096 2.066 3.0 Normal mode, SMPL_TIME 0x08 (fS 910 Hz) at 25C Fast mode, SMPL_TIME 0x07 (fS 1024 Hz) at 25C Sleep mode at 25C 3.3 11 36 500 130 3.6 14 42 750 128 Typ Max Unit V V Seconds Cycles Years s ms SPS SPS V mA mA A ms
TJ = 85C
Turn-On Time
1
This sensor relies on the earth's gravity to provide accurate incline angle measurements. The axis of rotation must be perpendicular to the earth's gravity to maintain the factory-calibrated accuracy of the sensor. Guaranteed by design. 3 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at -40C, +25C, +85C, and +125C. 4 Retention lifetime equivalent at junction temperature (TJ) 55C as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature.
2
Rev. 0 | Page 4 of 28
ADIS16203
TIMING SPECIFICATIONS
TA = +25C, VDD = 3.3 V, tilt = 0, unless otherwise noted. Table 2.
Parameter fSCLK tDATARATE tCS tDAV tDSU tDHD tDF tDR tSFS
1 2
Description Fast mode, SMPL_TIME 0x07 (fS 1024 Hz) Normal mode, SMPL_TIME 0x08 (fS 910 Hz) Chip select period, fast mode, SMPL_TIME 0x07 (fS 1024 Hz) Chip select period, normal mode, SMPL_TIME 0x08 (fS 910 Hz) Chip select to clock edge Data output valid after SCLK falling edge 2 Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge 3
Min 1 0.01 0.01 40 100 48.8 24.4 48.8
Typ
Max 2.5 1.0
100
5 5 5
12.5 12.5
Unit MHz MHz s s ns ns ns ns ns ns ns
Guaranteed by design, not production tested. The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
TIMING DIAGRAMS
tDATARATE tSTALL
CS
tSTALL = tDATARATE - 16/fSCLK
Figure 2. SPI Chip Select Timing
CS
tCS
1 SCLK 2 3 4 5 6 15 16
06108-002
SCLK
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A5
tDHD
A4 A3 A2 D2 D1 LSB
06108-003
Figure 3. SPI Timing, Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1
Rev. 0 | Page 5 of 28
ADIS16203 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered) Acceleration (Any Axis, Powered) VDD to COM Digital Input/Output Voltage to COM Analog Inputs to COM Operating Temperature Range Storage Temperature Range Rating 3500 g 3500 g -0.3 V to +7.0 V -0.3 V to +5.5 V -0.3 V to VDD + 0.3 V -40C to +125C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Package Characteristics
Package Type 16-Lead LGA JA 250C/W JC 25C/W Device Weight 0.6 g
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 28
ADIS16203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AUX ADC VREF
15 13 14 16 1
AUX DAC 12 NC 11 AUX COM 10 RST
9 8 7 6 5
COM
VDD
SCLK DOUT DIN CS
ADIS16203
BOTTOM VIEW (Not to Scale)
2
3
4
DIO1
AUX COM
NC
NC = NO CONNECT
DIO0
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6 7, 11 8, 10 9 12 13 14 15 16
1
Mnemonic SCLK DOUT DIN CS DIO0, DIO1 NC AUX COM RST AUX DAC VDD AUX ADC VREF COM
Type 1 I O I I I/O - S I O S I O S
Description SPI Serial Clock. SPI Data Out. SPI Data In. SPI Chip Select, Active Low. This input frames the serial data transfer. Multifunction Digital I/O Pin. No Connect. Auxiliary Grounds. Connect to GND for proper operation. Reset, Active Low. This input resets the embedded microcontroller to a known state. Auxiliary DAC Analog Voltage Output. +3.3 V Power Supply. Auxiliary ADC Analog Input Voltage. Precision Reference Output. Common. Reference point for all circuitry in the ADIS16203.
S = supply, O = output, I = input.
Rev. 0 | Page 7 of 28
06108-004
ADIS16203 TYPICAL PERFORMACE CHARACTERISTICS
30
90
25
80 70
POPULATION (%)
INCL_OUT (Degrees)
20
60 50 40 30 20 10
06108-008
15
10
5
-1.0
-0.8 -0.6 -0.4 -0.2
0
0.2
0.4
0.6
0.8
1.0
06108-032
0 ERROR (Degrees)
0 2.9
3.0
3.1
3.2
3.3 SUPPLY (V)
3.4
3.5
3.6
3.7
Figure 5. Inclination Error Distribution at 25C/3.3 V, Incline = 0
150
3.5 3.0 2.5
Figure 8. Self-Test Shift vs. Supply at 25C
125
100
INCL_OUT (Degrees)
QUANTITY
2.0 1.5 1.0
75
50
0.5 0 -0.5
25
0
-20 0 20 40 60 80 100 120
06108-006
TEMPERATURE (C)
(V/LSB)
Figure 6. Inclination Error vs. Temperature
80
0.40
Figure 9. ADC Gain Distribution at 25C/3.3 V
70
0.35
60
0.30
ERROR (Degrees)
0.25 0.20 0.15
QUANTITY
50 40 30 20
0.10
10
0.05
0
-2.4 -2.1 -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
06108-033
SUPPLY VOLTAGE (V)
(mV)
Figure 7. Inclination Error vs. Supply
Figure 10. ADC Offset Distribution at 25C/3.3 V
Rev. 0 | Page 8 of 28
06108-010
0 2.9
06108-009
-1.0 -40
607.6 607.8 608.0 608.2 608.4 608.6 608.8 609.0 609.2 609.4 609.6 609.8 610.0 610.2 610.4 610.6 610.8 611.0 611.2 611.4 611.6 611.8 612.0 612.2 612.4
ADIS16203
3
45 40
2
35
NONLINEARITY (LSB)
1
30
QUANTITY
1 4096 8192 ADC CODES 12288 16384
06108-011
25 20 15 10
0
-1
-2
5
-3
0
-2.7 -2.4 -2.1 -1.8 -1.5 -1.2 -0.9 -0.6 -0.3 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5
06108-014
(mV)
Figure 11. Typical ADC Integral Nonlinearity at 25C/3.3 V
3
5 4
Figure 14. DAC Offset Distribution at 25C/3.3 V
3.0V/-40C 3.0V/+25C 3.0V/+125C 3.3V /-40C 3.3V/+25C 3.3V/+125C 3.6V/-40C 3.6V/+25C 3.6V/+125C
2
3
NONLINEARITY (LSB)
NONLINEARITY (LSB)
1
2 1 0 -1 -2 -3 -4
0
-1
-2
06108-012
1
4096
8192 ADC CODES
12288
16384
0
512
1024
1536
2048
2560
3072
3584
4096
DAC CODES
Figure 12. Typical ADC Differential Nonlinearity
120
Figure 15. Typical DAC Integral Nonlinearity
250
100
200
80
QUANTITY
60
QUANTITY
150
100
40
50
20
06108-013
2.4975 2.4977 2.4979 2.4981 2.4983 2.4985 2.4987 2.4989 2.4991 2.4993 2.4995 2.4997 2.4999 2.5001 2.5003 2.5005 2.5007 2.5009 2.5011 2.5013 2.5015 2.5017 2.5019 2.5021 2.5023 (V)
0
0 606.6 606.9 607.2 607.5 607.8 608.1 608.4 608.7 609.0 609.3 609.6 609.9 610.2 610.5 610.8 611.1 611.4 611.7 612.0 612.3 612.6 612.9 613.2 613.5 613.8
06108-016
(V/LSB)
Figure 13. DAC Gain Distribution at 25C/3.3 V
Figure 16. VREF Distribution at 25C/3.3 V
Rev. 0 | Page 9 of 28
06108-015
-3
-5
ADIS16203
60 180 160 50 140 40
QUANTITY QUANTITY 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27
120 100 80 60 40
30
20
10 20 0
06108-017
0
370 378 386 394 402 410 418 426 434 442 450 458 466 474 482 490 498 506 514 522 530 538 546 554 562
06108-020
06108-022 06108-021
(C)
(A)
Figure 17. Temperature Distribution at 25C/3.3 V
140
Figure 20. Sleep Mode Power Supply Current Distribution at 25C/3.3 V
0.0010
120
SLEEP MODE CURRENT (A)
0.0008
100
QUANTITY
80 60
0.0006
0.0004
40
20 0
9.4 9.7
06108-018
0.0002
0 -50
10.0
10.3
10.6
10.9
11.2
11.5
11.8
12.1
12.4
12.7
13.0
-30
-10
10
30
50
70
90
110
130
150
(mA)
TEMPERATURE (C)
Figure 18. Normal Mode Power Supply Current Distribution at 25C/3.3 V
140 120
SLEEP MODE CURRENT (A)
Figure 21. Sleep Mode Current vs. Temperature at 3.3 V
0.0010
0.0008
100
QUANTITY
80
0.0006
60 40
0.0004
20 0
29.0 29.6 30.2 30.8 31.4 32.0 32.6 33.2 33.8 34.4 35.0 35.6 36.2 36.8 37.4 38.0 38.6 39.2 39.8 40.4 41.0 41.6 42.2 42.8 43.4
06108-019
0.0002
0 2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
(mA)
SUPPLY VOLTAGE (V)
Figure 19. Fast Mode Power Supply Current Distribution at 25C/3.3 V
Figure 22. Sleep Mode Current vs. Supply Voltage at 25C
Rev. 0 | Page 10 of 28
ADIS16203 THEORY OF OPERATION
The ADIS16203 is a calibrated digital inclinometer that provides a full 360 of measurement range in any rotational plane that is parallel to the earth's gravity. A dual-axis accelerometer provides the base-sensing function, which resolves the earth's gravity into two orthogonal vectors, as displayed in Figure 23. A power-efficient approach to a common trigonometric identity converts these orthogonal vectors into an inclineangle measurement.
1g
OUTPUT RESPONSE
The incline-angle measurements are linear with respect to degrees, and the sensor's orientation produces the output response displayed in Figure 25. This figure is helpful in understanding the basic orientation of the inertial sensor measurement axes.
INCL_OUT = 90 INCL_180_OUT = 90
INCL_OUT = 0 INCL_180_OUT = 0
a2 a1 1g
0
EARTH'S SURFACE
06108-036
BOTTOM VIEW (Not to Scale)
Figure 23. Sensor Measurement Diagram
INCL_OUT = 180 INCL_180_OUT = 180
The digital postprocessing circuit digitizes the sensor outputs and applies sensitivity/offset calibration coefficients prior to angle calculations. A factory calibration produces these coefficients using a full 360 mechanical rotational apparatus. This eliminates the need for system-level calibration in many cases. In addition to calibrating the sensor elements, the ADIS16203 corrects for power-supplydependent parameters, providing a more robust calibration. The accuracy of the incline-angle measurements relies on three important factors: the absence of external (aside from gravity) acceleration, managing offset errors introduced during system-level configuration, and maintaining a proper axis of rotation (rotation plane parallel with earth's gravity). All of these factors can influence the acceleration measurements and introduce error. The ADIS16203 provides a simple method for calibrating configuration errors by providing the INCL_NULL register function. See the Calibration section for more details. In addition, a 10 tilt plane error can introduce as much as 1 of error in the incline-angle outputs.
SYSTEM-LEVEL ORIENTATION OFFSET TILT PLANE ERROR
INCL_OUT = 270 INCL_180_OUT = -90 EARTH'S SURFACE
06108-023
Figure 25. Output Response vs. Orientation
TEMPERATURE SENSOR
An internal temperature sensor monitors the accelerometer's junction temperature. The TEMP_OUT data register provides a digital representation of this measurement. This sensor provides a convenient temperature measurement for system-level characterization and calibration feedback.
PCB ATTACHMENT OFFSET
IDEAL = 90
06108-038
EARTH'S SURFACE
Figure 24. ADIS16203 System-Level Orientation
Rev. 0 | Page 11 of 28
ADIS16203 BASIC OPERATION
The ADIS16203 is designed for simple integration into industrial system designs, requiring only a 3.3 V power supply and a 4-wire, industry standard SPI. The SPI port facilitates all data transfers with the ADIS16203's registers. Each ADIS16203 function (output data and programming control) has its own register that contains two bytes of data, and each byte of data has its own unique bit map. These two bytes are referred to as upper and lower bytes, and each has its own 6-bit address. SCLK have no impact on operation. A complete data frame contains 16 clock cycles. Because the SPI port operates in full duplex mode, it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT) functions during the same data frame. Figure 26 displays a typical data frame for writing a command to a control register. In this case, the first bit of the DIN sequence is a 1, followed by a 0, then the 6-bit address and 8-bit data command. Because each write command covers a single byte of data, two data frames are required when writing the entire 16-bit space of a register. Reading the contents of a register requires a modification to the sequence in Figure 26. In this case, the first two bits in the DIN sequence are 0, followed by the address of the register. Each register has two addresses, but either one can be used to access its entire 16 bits of data. The final eight bits of the DIN sequence are irrelevant and can be counted as don't cares during a read command. Then, during the next data frame, the DOUT sequence will contain the register's 16-bit data, as shown in Figure 27. Even though a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling.
SERIAL PERIPHERAL INTERFACE (SPI)
The ADIS16203's SPI port provides a common interface that is supported by a wide variety of digital platforms, including MCUs, DSPs, and FPGAs. Even when a dedicated port is not available, the SPI can be implemented using manual bit manipulation, which is more commonly known as bit banging. The purpose of this section is to provide a basic description of SPI operation in the ADIS16203. Please refer to Table 2, Figure 2, and Figure 3 for detailed timing and operation of this port. The ADIS16203's SPI port includes four signals: chip select (CS), serial clock (SCLK), data input (DIN), and data output (DOUT). The CS line enables the ADIS16203's SPI port and, in effect, frames each SPI event. When this signal is high, the DOUT lines are in a high impedance state and the signals on DIN and
CS
DATA FRAME
SCLK
DIN
W/R
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5 DC4
DC3
DC2
DC1
DC0
WRITE = 1 READ = 0
REGISTER ADDRESS
DATA FOR WRITE COMMANDS DON'T CARE FOR READ COMMANDS
Figure 26. DIN Bit Sequence
CS DATA FRAME DATA FRAME
SCLK
DIN W/R BIT
ADDRESS ZERO
DON'T CARE
NEXT COMMAND
DOUT
BASED ON PREVIOUS COMMAND
16-BIT REGISTER CONTENTS
Figure 27. SPI Sequence for Read Commands
Rev. 0 | Page 12 of 28
06108-024
06108-037
ADIS16203
DATA OUTPUT REGISTER ACCESS
The ADIS16203 provides access to two calibrated incline-angle measurements (+360 and 180 output formats), power supply measurements, temperature measurements, and an auxiliary 12-bit ADC channel. This output data is continuously updating internally, regardless of user read rates. The follow bit map describes the structure of all output data registers in the ADIS16203.
MSB ND D7 EA D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0
The MSB holds the new data (ND) indicator. When the output registers are updated with new data, the ND bit goes to a 1 state. After the output data is read, it returns to a 0 state. The EA bit is used to indicate an alarm condition, which could result from a number of conditions, such as a power supply that is out of the specified operating range. See the Alarms section for more details. The output data is either 12 or 14 bits in length. For all of the 12-bit output data, the D13 and D12 bits are assigned don't care status. The output data register map is located in Table 6 and provides all of the necessary details for accessing each register's data. Table 7 displays the output coding for the 180 output data register, INCL_180_OUT, and Figure 28 displays a timing diagram example for reading this register.
Table 6. Data Output Register Information
Name SUPPLY_OUT AUX_ADC TEMP_OUT INCL_OUT INCL_180_OUT Function Power supply data Auxiliary analog input data Sensor temperature data Inclination data 180 inclination data Address 0x03, 0x02 0x09, 0x08 0x0B, 0x0A 0x0D, 0x0C 0x0F, 0x0E Resolution (Bits) 12 12 12 14 14 Data Format Binary Binary Binary Binary Twos complement Scale Factor (per LSB) 1.22 mV 0.61 mV -0.47C 0.025 0.025
Table 7. Output Coding Example, INCL_180_OUT 1, 2
Acceleration Level +170.10 +93.05 +0.625 0.00 -0.625 -93.05 -170.10
1 2
Binary Output 01 1010 1001 0100 00 1110 1000 1010 00 0000 0001 1001 00 0000 0000 0000 11 1111 1110 0111 11 0001 0111 0110 11 1100 0001 1000
Hex Output 0x1A94 0x0E8A 0x0019 0x0000 0x3FE7 0x3176 0x256C
Decimal +6804 +3722 +25 0 -25 -3722 -6804
Two MSBs have been masked off and are not considered in the coding. Nominal sensitivity (0.025/LSB) and zero offset null performance are assumed.
CS
SCLK
DIN W/R BIT = 0 ADDRESS = 001111 W/R BIT = 0 ADDRESS = 001111 OR 0x0F
DOUT DATA = 1000111010001010 NEW DATA, NO ALARM, INCL_180_OUT = +93.05
06108-025
Figure 28. SPI Sequence Reading INCL_OUT When Incline Angle = 93.05
Rev. 0 | Page 13 of 28
ADIS16203 PROGRAMMING AND CONTROL
CONTROL REGISTER OVERVIEW
The ADIS16203 offers many programmable features that are controlled by writing commands to the appropriate control registers using the SPI. For added system flexibility and programmability, the following sections describe these controls and specify each register's configuration. A list of features that are available for configuration in this register space follows: * * * * * * * * * * Calibration: Automatic offset null, manual offset adjustment, factory reset Rotational direction: clockwise or counter-clockwise Sample rate adjustment Filter response optimization Alarm settings: threshold or rate of change, and comparison with filtered or unfiltered data I/O configuration: data ready, etc. Power management: sleep mode, normal and high performance modes Auxiliary DAC level setting Status checks: verify power supply, SPI communication, package orientation FlashTM updates to store configuration
CONTROL REGISTER ACCESS
Table 8 displays the control register map for the ADIS16203, including address, volatile status, basic function, and accessibility (read/write). The following sections contain detailed descriptions and configurations for each of these registers. The ADIS16203 is a Flash-based device with the nonvolatile functional registers implemented as Flash registers. Take into account the endurance limitation of 20,000 writes when considering the system-level integration of these devices. The nonvolatile column in Table 8 indicates the registers that are recovered on powerup. The user must use a manual Flash update command (using the command register) to store the nonvolatile data registers once they are configured properly. When performing a manual Flash update command, the user needs to ensure that the power supply remains within limits for a minimum of 50 ms after the start of the update. This ensures a successful write of the nonvolatile data.
Table 8. Control Register Mapping
Register Name INCL_NULL ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL AUX_DAC GPIO_CTRL MSC_CTRL SMPL_TIME AVG_CNT SLP_CNT STATUS COMMAND Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Nonvolatile X X X X X X Address 0x00 to 0x01 0x18 0x20 0x22 0x24 0x26 0x28 0x2A to 0x2F 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E Bytes 2 2 2 2 2 2 2 6 2 2 2 2 2 2 2 2 Function Reserved Incline null calibration Alarm 1 amplitude threshold Alarm 2 amplitude threshold Alarm 1 sample period Alarm 2 sample period Alarm source control register Reserved Auxiliary DAC data Auxiliary digital I/O control register Miscellaneous control register ADC sample period control Defines number of samples used by moving average filter Counter used to determine length of power-down mode System status register System command register
X X X
Rev. 0 | Page 14 of 28
ADIS16203 CONTROL REGISTER DETAILS
All ADIS16203 control registers are organized into 2-byte segments, and both upper (Bit 8 to Bit 15) and lower (Bit 0 to Bit 7) bytes have unique addresses and can be accessed individually.
MSB D15 D7 D14 D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0
CALIBRATION REGISTER DEFINITION
INCL_NULL Register Definition
Address 0x19, 0x18
1
Scale1 0.025
Default 0x0000
Format Binary
Access R/W
Scale is the weight of each LSB.
This section provides a description of each register, including its purpose, relevant scaling information, bit maps, addresses, and default values.
The INCL_NULL register is the user controlled register for calibrating system-level inclination offset errors. The maximum calibration range is +0 to +359.975 or 0 to +14,399 decimal codes. The contents of this register are nonvolatile. Table 10. INCL_NULL Bit Designations
Bit 15:14 13:0 Description Not necessary, force to 0 Data bits
CALIBRATION
In addition to the factory calibration, the ADIS16203 provides two user calibration options. Both options utilize the INCL_NULL control register, which provides an add function to the two inclineangle output registers: INCL_OUT and INCL_180_OUT. Because the default contents of INCL_NULL are 0, adding it to these two outputs has no effect on the output data. The first calibration option is an automatic null function. This function measures the contents of INCL_OUT and then writes the inverse of this value into the INCL_NULL control register. The accuracy of this calibration is dependent on the stability of the INCL_OUT measurement; therefore, maximizing the filtering will minimize the errors associated with noise. Table 9 displays a sequence that executes the automatic null. Table 9. Automatic Null Sequence
Step Write 0x08 to Address 0x38 Wait for 512 samples Write 0x01 to Address 0x3E Description Sets averaging count to 256 using the AVG_CNT register Waits for the lowest noise data Executes the global autonull function using the COMMAND register
ALARMS
The ADIS16203 contains two independent alarm functions that are referred to as Alarm 1 and Alarm 2. The Alarm 1 function is managed by the ALM_MAG1 and ALM_SMPL1 control registers. The Alarm 2 function is managed by the ALM_MAG2 and ALM_SMPL2 control registers. Both the Alarm 1 and Alarm 2 functions share the ALM_CTRL register. For simplicity, this section refers to the Alarm 1 functionality only. The 16-bit ALM_CTRL register serves several roles in controlling the Alarm 1 function. First, it is used to enable the overall Alarm 1 function and to select the output data variable that is to be monitored for the alarm condition. Second, it is used to select whether the Alarm 1 function is based upon a predefined threshold (THR) level or a predefined rate-of-change (ROC) slope. Third, the ALM_CTRL register can be used in setting up one of the two general-purpose input/output lines (GPIOs) to serve as a hardware output that indicates when an alarm condition has occurred. Enabling the I/O alarm function as well as setting its polarity and controlling its operation are accomplished using this register. Fourth, this register provides the controls for setting the comparison data as filtered or unfiltered. Note that when enabled, the hardware output indicator serves both the Alarm 1 and Alarm 2 functions and cannot be used to differentiate between one alarm condition and the other. It is simply used to indicate that an alarm is active and that the user should poll the device via the SPI to determine the source of the alarm condition (see the STATUS Register Definition section). Because the ALM_CTRL, MSC_CTRL, and GPIO_CTRL control registers can influence the same GPIO pins, a priority level has been established to avoid conflicting assignments of the two GPIO pins. This priority level is defined as MSC_CTRL, which has precedence over ALM_CTRL, which has precedence over GPIO_CTRL.
Restore previous average count
Increasing the sample rate using the SMPL_TIME control register will minimize the waiting time if this parameter is critical. The second option for system-level calibration is manual adjustment. The INCL_NULL control register can be updated using write commands. Refer to its definition in the INCL_NULL Register Definition section for details. The factory calibration can be restored by writing 0x02 to Register Address 0x3E. This restores INCL_NULL to 0.
Rev. 0 | Page 15 of 28
ADIS16203
The ALM_MAG1 control register used in controlling the Alarm 1 function has two roles. The first role is to store the value with which the output data variable is compared against to discern if an alarm condition exists. The second role is to identify whether the alarm should be active for excursions above or below the alarm limit. If 1 is written to Bit 15 of the ALM_MAG1 control register, the alarm is active for excursions extending above a given limit. If 0 is written to Bit 15, the alarm is active for excursions dropping below the given limit. The comparison value contained within the ALM_MAG1 control register is located within the lower 14 bits. The monitored output register establishes the format of the 14-bit data space in the ALM_MAG1 and ALM_MAG2 registers. For example, setting the alarm to monitor INCL_OUT sets the data format to a 14-bit, twos complement number, which carries a bit weight of 0.025. Use caution when monitoring the temperature output register for the alarm conditions. Here, the negative temperature scale factor results in the greater than and less than selections requiring reverse logic. Setting Bit 11 in the ALM_CTRL register establishes the mode of operation: threshold or rate of change (ROC). When the ROC function is enabled, the comparison of the output data variable is against the ALM_MAG1 level averaged over the number of samples as identified in the ALM_SMPL1 control register. This acts to create a comparison of ( units/ time) or the derivative of the output data variable against a predefined slope. The versatility built into the alarm function allows the user to adapt to several applications. For example, in the case of monitoring twos complement variables, Bit 15 within the ALM_MAG1 control register can allow for the detection of negative excursions below a fixed level. In addition, the Alarm 1 and Alarm 2 functions can be set to monitor the same variable that allows the user to discern if an output variable remains within a predefined window. Another potential ROC application is to monitor slowly changing outputs in the inclination level. With the addition of the alarm hardware functionality, the ADIS16203 can be left to run independently of the main processor and interrupt the system only when an alarm condition occurs. Conversely, the alarm condition can be monitored through the routine polling of any one of the seven data output registers.
14 13:0
Bits 4 and 5 in the ALM_CTRL register establishes whether ALM_MAG1 and ALM_MAG2 are compared with filtered or unfiltered data.
ALM_MAG1 Register Definition
Address 0x21, 0x20
1 2
Default1 0x0000
Format2 N/A
Access R/W
Default is valid only until the first register write cycle. Format is established by source of monitored data
The ALM_MAG1 register contains the threshold level for Alarm 1. The contents of this register are nonvolatile. Table 11. ALM_MAG1 Bit Designations
Bit 15 Description Greater than Active Alarm Bit. 1: Alarm is active for an output greater than ALM_MAG1 register setting. 0: Alarm is active for an output less than ALM_MAG1 register setting. Not used. Data Bits. This number can be either twos complement or straight binary. The format is set by the value being monitored by this function.
ALM_SMPL1 Register Definition
Address 0x25, 0x24
1
Default1 0x0000
Format Binary
Access R/W
Default is valid only until the first register write cycle.
The ALM_SMPL1 register contains the sample period information for Alarm 1, when it is set for ROC alarm monitoring. The ROC alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the ALM_MAG1 register. The contents of this register are nonvolatile. Table 12. ALM_SMPL1 Bit Designations
Bit 15:8 7:0 Description Not used Data bits
Rev. 0 | Page 16 of 28
ADIS16203
ALM_MAG2 Register Definition
Address 0x23, 0x22
1 2
Table 15. ALM_CTRL Bit Designations
2
Default 0x0000
1
Format N/A
Access R/W
Bit 15
Value
Default is valid only until the first register write cycle. Format is established by source of monitored data.
14:12 000 001 010 011 100 101 110 111 11
The ALM_MAG2 register contains the threshold level for Alarm 2. The contents of this register are nonvolatile. Table 13. ALM_MAG2 Bit Designations
Bit 15 Description Greater than Active Alarm Bit. 1: Alarm is active for an output greater than ALM_MAG2 register setting. 0: Alarm is active for an output less than ALM_MAG2 register setting. Not used. Data Bits. This number can be either twos complement or straight binary. The format is set by the value being monitored by this function.
14 13:0
10:8 000 001 010 011 100 101 110 111 7:6 5
ALM_SMPL2 Register Definition
Address 0x27, 0x26
1
Default1 0x0000
Format Binary
Access R/W
Default is valid only until the first register write cycle.
The ALM_SMPL2 register contains the sample period information for Alarm 2, when it is set for ROC alarm monitoring. The ROC alarm function averages the change in the output variable over the specified number of samples and compares this change directly to the values specified in the ALM_MAG2 register. The contents of this register are nonvolatile. Table 14. ALM_SMPL2 Bit Designations
Bit 15:8 7:0 Description Not used Data bits
4
3 2
1
ALM_CTRL Register Definition
Address 0x29, 0x28
1
Default1 0x0000
Format N/A
Access R/W
0
Description Rate of Change (ROC) Enable for Alarm 2 1: ROC is active 0: ROC is inactive Alarm 2 Source Selection Alarm disable Alarm source: power supply output Not used Not used Alarm source: auxiliary ADC output Alarm source: temperature sensor output Alarm source: INCL_OUT output Alarm source: INCL_180_OUT output Rate of Change (ROC) Enable for Alarm 1 1: ROC is active 0: ROC is inactive Alarm 1 Source Selection Alarm disable Alarm source: power supply output Not used Not used Alarm source: auxiliary ADC output Alarm source: temperature sensor output Alarm source: INCL_OUT output Alarm source: INCL_180_OUT output Not used ADF2--Alarm Data Filter 1: Use filtered data for comparison 0: Use instantaneous data for comparison ADF1--Alarm Data Filter 1: Use filtered data for comparison 0: Use instantaneous data for comparison Not used Alarm Output Enable 1: Alarm output enabled 0: Alarm output disabled Alarm Output Polarity 1: Active high 0: Active low Alarm Output Line Select 1: DIO1 0: DIO0
Default is valid only until the first register write cycle.
The ALM_CTRL register contains the alarm control variables.
Rev. 0 | Page 17 of 28
ADIS16203
SAMPLE PERIOD CONTROL
The output data variables within the ADIS16203 are sampled and updated at a rate based upon the SMPL_TIME control register. The sample period can be precisely controlled over more than a threedecade range using a time base with two settings and a 7-bit binary count. The use of a time base that varies with a ratio of 1:31 allows for a more optimum resolution in the sample period than a straight binary counter. This is reflected in Figure 29, where the frequency is presented on a logarithmic scale. Note that the sample period given is defined as the cumulative time required to sample, process, and update all data output variables. The data output variables are sampled as a group and in unison with one another. Whatever update rate is selected for one signal, all output data variables are updated at the same rate whether they are monitored via the SPI or not. For a sample period setting of less than 1098.9 s (SMPL_TIME 0x07), the overall power dissipation in the part rises by approximately 300%.
256
Table 16. SMPL_TIME Bit Descriptions
Bit 15:8 7 Description Not used. ADC Time Base Control. The MSB and TMBS set the time base of the acquisition system to 122.1 s when SR7 = 0 vs. 3.784 ms when SR7 = 1. ADC Sample Period Count. The lower seven bits, SP6 to SP0, represent a binary count that results in the combined sample period of the ADC when added to one and then multiplied by the time base. (The combined sample period is the period required to sample and update all seven data outputs.) The minimum setting for the lower seven bits, SP6 to SP0, is 0x01. The overall acquisition time can be varied from 244.2 s to 15.51 ms in 122.1 s increments for TMBS = 0 and from 7.57 ms to 481 ms in 3.784 ms increments for TMBS = 1. This equates to the sample rate varying from 4096 SPS to 64.5 SPS for TMBS = 0 and from 132 SPS to 2.08 SPS for TMBS = 1.
6:0
FILTERING CONTROL
The ADIS16203 uses two types of filters for the output data. The INCL_OUT and INCL_180_OUT data outputs use a Bartlett Window function, and the SUPPLY_OUT, AUX_ADC, and TEMP_OUT data outputs use a standard moving-averaging filter. The number of taps set by the AVG_CNT control register establishes the frequency response. The number of taps can be derived from the contents of AVG_CNT using the following equation:
N = 2 AVG _ CNT
192
SMPL_TIME VALUE
128
64
1
10
100 FREQUENCY (Hz)
1k
10k
06108-026
0
The following equations characterize the expected behavior of each filtering approach. Figure 30 and Figure 31 shows the frequency responses of each filter approach. Averaging:
HA( f ) = sin( x N x f x t s ) N x sin( x f x t s )
Figure 29. SMPL_TIME Values vs. Sample Frequency
SMPL_TIME Register Definition
Address 0x37, 0x36
1
Default1 0x0008
Format N/A
Access R/W
Bartlett Window:
2 HB (f )= HA( f )
Default is valid only until the first register write cycle.
The data within this register is nonvolatile, allowing for data recovery upon reset.
The primary difference in the frequency responses offered by each approach lies in their side lobes, which are 13 dB better in the Bartlett Windowing approach. The Bartlett Window filtering has two times the latency of the moving average filter.
Rev. 0 | Page 18 of 28
ADIS16203
20 CORE SENSOR RESPONSE
POWER-DOWN CONTROL
AVG_CNT = 1 N=2
0
AVG_CNT = 4 N = 16 -20 AVG_CNT = 8 N = 256 -40
1
10
100 FREQUENCY (Hz)
1000
10000
06108-034
-60
The ADIS16203 has the ability to power down for user-defined amounts of time, using the SLP_CNT control register. The amount of time specified by the SLP_CNT control register is equal to the binary count of the 8-bit control word multiplied by 0.5 sec. Therefore, the 255 codes cover an overall shutdown period of 127.5 seconds. The SLP_CNT register is volatile and is set to 0 upon both power-up and subsequent wake-ups from the power-down period. By setting the SLP_CNT control register to a nonzero state, the ADIS16203 automatically powers down once the next sample period is completed and the data output registers are updated. Once the ADIS16203 is placed into power-down mode, it can only return to normal operation by timing out, by a reset command (using the RST hardware control line), or by cycling the power applied to the part. Once awake, the data output registers can be scanned to determine what the state of the output registers were prior to powering down. Once the data is recovered, the device can be powered down again by simply writing a nonzero value to the SLP_CNT control register and starting the process over. Once the power-down time is complete, the recovery time for the ADIS16203 is approximately 2 ms. This recovery time is implemented within the device to allow for recovery of the ADC prior to performing the next data conversion. Note that the ND data bit within the data output control registers is cleared when the ADIS16203 is powered down. Likewise, the new data hardware I/O line is placed into an inactive state prior to being powered down. The DAC is placed into a power-down mode as well, resulting in the DAC output dropping to 0 V during the power-down period. All control register settings are retained while powered down with the exception of the SLP_CNT control register.
ATTENUATION (dB)
Figure 30. INCL_OUT, INCL_180_OUT Filter Response
20
0
AVG_CNT = 1 N=2 AVG_CNT = 4 N = 16
ATTENUATION (dB)
-20 AVG_CNT = 8 N = 256 -40
1
10
100 FREQUENCY (Hz)
1000
10000
Figure 31. SUPPLY_OUT, AUX_ADC, and TEMP_OUT Filter Response, fS = 4096 SPS
AVG_CNT Register Definition
Address 0x39, 0x38
1
Default1 0x0007
Format Binary
Access R/W
06108-035
-60
SLP_CNT Register Definition
Address 0x3B, 0x3A
1
Default is valid only until the first register write cycle.
Default1 0x0000
Format Binary
Access R/W
The AVG_CNT register contains information that represents the number of averages to be applied to the output data. The number of averages can be calculated by powers of 2. The number of averages can be set to 1, 2, 4, 8, 16, 32, 64, 128, or 256. Table 17. AVG_CNT Bit Description
Bit 15:4 3:0 Description Not used Data bits (maximum = 1000, or a decimal value of 8)
Default is valid only until the first register write cycle.
Table 18. SLP_CNT Bit Descriptions
Bit 15:8 7:0 Description Not used Data bits
Rev. 0 | Page 19 of 28
ADIS16203
STATUS FEEDBACK
The status control register within the ADIS16203 is utilized in determining the present state of the device. The ability to monitor the device becomes necessary when and if the ADIS16203 has registered an alarm and/or error condition as indicated by the alarm enable (Bit 14) within the output data registers.
COMMAND CONTROL
The COMMAND control register is utilized in sending global commands to the ADIS16203 device. Any one of the global commands can be implemented by simply writing 1 to its corresponding bit location. The command control register has write-only capability and is volatile. Table 20 describes each of these global commands.
STATUS Register Definition
Address 0x3D, 0x3C
1
Default1 0x0000
Format N/A
Access Read only
COMMAND Register Definition
Address 0x3F, 0x3E
1
Default is valid only until the first register write cycle.
Default1 0x0000
Format N/A
Access Write only
Default is valid only until the first register write cycle.
The STATUS control register contains the alarm/error flags that indicate abnormal operating conditions. See Table 19 for each bit's definition. Bit 0 and Bit 1 will automatically clear when the power supply is in the specified range of operation. Setting Bit 4 in the COMMAND register clears all flags. The flags are set on a continuing basis as long as the error or alarm conditions persist. Table 19. STATUS Bit Descriptions
Bit 15:10 9 Description Not used Alarm 2 Status 1: Active 0: Normal mode Alarm 1 status 1: Active 0: Normal mode Not used Invalid Orientation 1: Invalid orientation 0: Normal mode Self Test Fail 1: Self-test failure 0: Self-test pass SPI Communications Failure 1: Error condition 0: Normal mode Control Register Update Failed 1: Error condition 0: Normal mode. Power Supply Above 3.625 V 1: Error condition 0: Normal mode Power Supply Below 2.975 V 1: Error condition 0: Normal mode
Table 20. COMMAND Bit Descriptions
Bit 15:8 7 6:5 4 3 Description Not used. Software Reset Command. Not used. Clear Status Register, once per activation Manual Flash Update Command. This command is utilized in updating all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash. Auxiliary DAC Latch Command. This command acts to latch the AUX_DAC control register data into the auxiliary DAC upon receipt of the command. This allows for sequential loading of the upper and lower AUX_DAC data bytes via the SPI without having the auxiliary DAC transition into unwanted, intermediate states based upon the individual AUX_DAC data bytes. Once the two bytes of AUX_DAC are loaded, the DAC latch command is initiated to move the data into the auxiliary DAC itself. Factory Reset Command. This command allows the user to reset the INCL_NULL register to its nominal setting (0x0000) upon receipt of the command. Data within the moving average filters is reset. As the manual Flash command (COMMAND register, Bit 3), this command stores all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash. Null Command. This command loads the inclination offset register with a value that zeros out the inclination and outputs. Useful as a single command to simultaneously zero the inclination outputs. As the manual Flash command (COMMAND register, Bit 3), this command stores all of the nonvolatile registers to Flash. Once the command is initiated, the supply voltage, VDD, must remain within specified limits for 50 ms to ensure proper update of the nonvolatile registers to Flash.
8
2
7 6
5
1
3
2
1
0
0
Rev. 0 | Page 20 of 28
ADIS16203
MISCELLANEOUS CONTROL REGISTER
The MSC_CTRL control register governs the operation of several miscellaneous features: using the general purpose I/O for data-ready (DR) hardware I/O function, reversing the polarity of rotation (clockwise vs. counter clockwise), and self-test. The control bits for each of these functions are described in Table 21. The operation of the data-ready hardware I/O function is very similar to the alarm hardware I/O function (controlled through the ALM_CTRL control register). In this case, the MSC_CTRL register can be used in setting up one of the GPIO pins to serve as the hardware output pin that indicates when the sampling, conversion, and processing of the data output variables have been completed. This register provides the ability to enable the data-ready hardware function and establish its polarity. The data-ready hardware I/O pin is reset automatically to an inactive state part way through the next conversion cycle, resulting in a pulse train with a duty cycle varying from ~15% to 35%, depending upon the sample period setting. Upon completion of the next data processing cycle, the data ready hardware I/O line is set to 1. The MSC_CTRL, ALM_CTRL, and GPIO_CTRL control registers can influence the same GPIO pins. A priority level has been established to avoid conflicting assignments of the two GPIO pins. This priority level is defined as MSC_CTRL and has precedence over ALM_CTRL, which has precedence over GPIO_CTRL. The self-test operation exercises the base accelerometer's mechanical structure and establishes a mechanical diagnostic test. The self-test offers the ability to have the ADIS16203 run an internal diagnostic test, which returns a pass/fail condition (see the STATUS register definition of Bit 5 in Table 19). This feature also provides the ability to observe the incline angle outputs during the self-test function, which is nominally 37, regardless of the incline angle of the device. Note that a self-test changes the contents of SMPL_TIME to improve the speed of this test. Upon completion, the ADIS16203 restores the original contents to SMPL_TIME.
MSC_CTRL Register Definition
Address 0x35, 0x34
1
Default1 0x0000
Format N/A
Access R/W
Default is valid only until the first register write cycle.
The 16-bit miscellaneous control register is used in the controlling of the self-test and data-ready hardware functions. This includes turning on and off the self-test function, as well as configuring the data-ready function. For the data-ready function, the written values are nonvolatile, allowing for data recovery upon reset. The self-test data is volatile and is set to 0s upon reset. This register has read/write capability. Table 21. MSC_CTRL Bit Descriptions
Bit 15:11 10 Description Not used No Self-Test on Power-Up 1: No self-test on power-up or reset 0: Self-test on power-up enabled (typically requires approximately 13 ms in high performance mode and approximately 35 ms in low power mode with every power-up or reset) Reverse Rotation 1: Reverses rotation of both inclination outputs 0: Normal operation Self-Test Enable 1: ST enabled (continuous self-test) 0: ST disabled Not used Data-Ready Enable 1: DR enabled 0: DR disabled Data-Ready Polarity 1: Active high 0: Active low Data-Ready Line Select 1: DIO1 0: DIO0
9
8
7:3 2
1
0
Rev. 0 | Page 21 of 28
ADIS16203 PERIPHERALS
AUXILIARY ADC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC into the ADIS16203 to digitize other system-level analog signals. The output of the ADC can be monitored through the AUX_ADC control register, as defined in Table 6. The ADC consists of a 12-bit successive approximation converter. The output data is presented in straight binary format with the full-scale range extending from 0 V to VREF. A high precision, low drift, factory-calibrated 2.5 V reference is also provided. Figure 32 shows the equivalent circuit of the analog input structure of the ADC. The input capacitor, C1, is typically 4 pF and can be attributed to parasitic package capacitance. The two diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward-biased and to start conducting. These diodes can handle 10 mA without causing irreversible damage to the part. The resistor is a lumped component that represents the on resistance of the switches. The value of this resistance is typically 100 . Capacitor C2 represents the ADC sampling capacitor and is typically 16 pF.
VDD D C1 R1 C2
06108-028
AUXILIARY DAC FUNCTION
The auxiliary DAC function integrates a standard 12-bit DAC into the ADIS16203. The DAC output is buffered and fed off-chip to allow for the control of miscellaneous system-level functions. Data downloads through the writing of two adjacent data bytes as defined in its register definition. To prevent the DAC from transitioning through inadvertent states during data downloads, a single command is used to simultaneously latch both data bytes into the DAC after they have been written into the AUX_DAC control register. This command is implemented by writing 1 to Bit 2 of the command control register and, once received, results in the DAC output transitioning to the desired state. The DAC output provides an output range of 0 V to 2.5 V. The DAC output buffer features a true rail-to-rail output stage. This means that, unloaded, the output is capable of reaching within 5 mV of ground. Moreover, the DAC's linearity performance (when driving a 5 k resistive load to ground) is good through the full transfer function, except for Code 0 to Code 100. Linearity degradation near ground is caused by saturation of the output amplifier. As the output is forced to sink more current, the nonlinear region at the bottom of the transfer function becomes larger. Larger current demands can significantly limit output voltage swing.
D
AUX_DAC Register Definition
Address 0x31, 0x30
1
Figure 32. Equivalent Analog Input Circuit Conversion Phase: Switch Open Track Phase: Switch Closed
Default1 0x0000
Format Binary
Access R/W
Default is valid only until the first register write cycle.
For ac applications, removing high frequency components from the analog input signal is recommended through the use of an RC lowpass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. When no input amplifier is used to drive the analog input, the source impedance should be limited to values less than 1 k. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated.
The AUX_DAC register controls the DAC function of the ADIS16203. The data bits provide a 12-bit binary format number, with 0 representing 0 V and 0x0FFFh representing 2.5 V. The data within this register is volatile and is set to 0s upon reset. This register has read/write capability. Table 22. AUX_DAC Bit Descriptions
Bit 15:12 11:0 Description Not used Data bits
Rev. 0 | Page 22 of 28
ADIS16203
GENERAL-PURPOSE I/O CONTROL
As previously noted, the ADIS16203 provides two general-purpose, bidirectional I/O pins (GPIOs) that are available to the user for control of auxiliary circuits within the target application. All I/O pins are 5 V tolerant, meaning that the GPIOs support an input voltage of 5 V. Each GPIO pin has an internal pull-up resistor of approximately 100 k and a drive capability of 1.6 mA. The direction, as well as the logic level, can be controlled for these GPIO pins through the GPIO_CTRL control register, as defined in Table 23. These same GPIO pins are also controllable through the ALM_CTRL and MSC_CTRL control registers. The priority for these three control registers in controlling the two GPIO pins is MSC_CTRL has precedence over ALM_CTRL, which has precedence over GPIO_CTRL. Table 23. GPIO_CTRL Bit Descriptions
Bit 15:10 9 Description Not used General-Purpose I/O Line 0, Data Direction Control 0: Input 1: Output General-Purpose I/O Line 1, Data Direction Control 0: Input 1: Output Not used General-Purpose I/O Line 0 Polarity 0: Low 1: High General-Purpose I/O Line 1 Polarity 0: Low 1: High
8
7:2 1
0
GPIO_CTRL Register Definition
Address 0x33, 0x32
1
Default1 0x0000
Format N/A
Access R/W
Default is valid only until the first register write cycle.
The data within the general-purpose digital I/O control register is volatile and is set to 0s upon reset.
Rev. 0 | Page 23 of 28
ADIS16203 APPLICATIONS
HARDWARE CONSIDERATIONS
The ADIS16203 can be operated from a single 3.3 V (3.0 V to 3.6 V) power supply. The ADIS16203 integrates two decoupling capacitors that are 1 F and 0.1 F in value. For the local operation of the ADIS16203, no additional power supply decoupling capacitance is required. However, if the system power supply presents a substantial amount of noise, additional filtering may be required. If additional capacitors are required, connect the ground terminal of each capacitor directly to the underlying ground plane. Finally, note that all analog and digital grounds should be referenced to the same system ground reference point.
SELF-TEST TIPS
When using the ADIS16203's self-test function to monitor incline angles around 0, using the INCL_180_OUT register is more convenient than using the INCL_OUT register. Because the measurements in the INCL_OUT register jump from 0 to 359.975, they may trigger false alarms. The same philosophy can be applied to monitoring conditions around 180. Because the INCL_OUT provides continuous measurements through 180 and the INCL_180_OUT abruptly changes from -180 to +180, the INCL_OUT register is a more convenient choice.
BAND GAP REFERENCE
The ADIS16203 provides an on-chip band gap reference of 2.5 V that is utilized by the on-board ADC and DAC. This internal reference also appears on the VREF pin. This reference can be connected to external circuits in the system. An external buffer would be required because of the low drive capability of the VREF output.
GROUNDING AND BOARD LAYOUT RECOMMENDATIONS
Maintaining low impedance signal return paths can be very critical in managing system-level noise effects. For best results, use a single, continuous ground plane that is tied to each ADIS16203 ground pin via short trace lengths. In addition to maintaining a low impedance ground structure, routing the SPI signals away from sensitive analog circuits, such as the ADC and DACs (if they are in use), can help mitigate system-level noise risks.
Rev. 0 | Page 24 of 28
ADIS16203
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented internally to the ADIS16203. For VDD below 2.35 V, the internal POR holds the ADIS16203 in reset. As VDD rises above 2.35 V, an internal timer times out for typically 130 ms before the part is released from reset. The user must ensure that the power supply has reached a stable 3.0 V minimum level by this time. Likewise, on power-down, the internal POR holds the ADIS16203 in reset until VDD drops below 2.35 V. Figure 33 illustrates the operation of the internal POR in detail.
2.35V TYP VDD 130ms TYP
Table 24.
Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (ts) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tp) Ramp-Down Rate Time 25C to Peak Temperature Condition Sn63/Pb37 Pb-Free 3C/sec max 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec 150C 200C 60 sec to 150 sec 3C/sec
POR
Figure 33. Internal Power-On Reset Operation
Once the power sequence is complete, the self-test sequence follows. This sequence takes approximately 14 ms in high performance mode and approximately 36 ms in normal mode. The power-up self-test can be disabled using Bit 10 in the MSC_CTRL register if the start time is a critical consideration.
183C 60 sec to 150 sec 240C + 0C/-5C 10 sec to 30 sec 6C/sec max 6 minutes max
217C 60 sec to 150 sec 260C + 0C/-5C 20 sec to 40 sec 6C/sec max 8 minutes max
SECOND-LEVEL ASSEMBLY
The ADIS16203 can be attached to the second-level assembly board using SN63 (or equivalent) or lead-free solder. Figure 34 and Table 24 provide acceptable solder reflow profiles for each solder type. Note that these profiles may not be the optimum profile for the user's application. In no case should 260C be exceeded. It is recommended that the user develop a reflow profile based upon the specific application. In general, the lowest peak temperature and shortest dwell time above the melt temperature of the solder result in less shock and stress to the product. In addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly.
TP RAMP-UP
TEMPERATURE
06108-029
EXAMPLE PAD LAYOUT
1.178 BSC (8 PLCS)
0.670 BSC (12 PLCS)
7.873 BSC (2 PLCS) 1.127 BSC (16 PLCS)
06108-031
tP
CRITICAL ZONE TL TO TP
0.500 BSC (16 PLCS)
Figure 35. Example Pad Layout
TL
TSMAX TSMIN
tL
tS
PREHEAT
RAMP-DOWN
t25C TO PEAK
TIME
Figure 34. Acceptable Solder Reflow Profiles
Rev. 0 | Page 25 of 28
06108-030
ADIS16203 OUTLINE DIMENSIONS
9.327 MAX SQ 1.405 BSC
13 12
A1 CORNER INDEX AREA
16 1
0.797 BSC
1.00 BSC
9 8 5 4
TOP VIEW
BOTTOM VIEW
0.227 BSC (4 PLCS)
0.373 BSC (16 PLCS)
5.00 TYP
3.90 MAX
030906-A
SIDE VIEW
Figure 36. 16-Terminal Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16203CCCZ 1 ADIS16203/PCBZ1
1
Temperature Range -40C to +125C
Package Description 16-Terminal Land Grid Array [LGA] Evaluation Board
Package Option CC-16-2
Z = Pb-free part.
Rev. 0 | Page 26 of 28
ADIS16203
NOTES
Rev. 0 | Page 27 of 28
ADIS16203
NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06108-0-8/06(0)
Rev. 0 | Page 28 of 28

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